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NX2142/2142A
SINGLE CHANNEL PWM CONTROLLER WITH FEEDFORWARD AND 5V BIAS REGULATOR
ADVANCE DATA SHEET Pb Free Product n The NX2142/2142A controller IC is a compact synchron nous Buck controller IC with 10 lead MSOP package n designed for step down DC to DC converter applications with voltage feedforward functionality. Voltage n feedforward provides fast response, good line regulan tion and nearly constant power stage gain under wide n voltage input range. The NX2142/2142A controller is n optimized to convert single supply up to 24V bus voltn age to as low as 0.8V output voltage. NX2142/2142A n can function as a single supply controller with its 5V bias regulator. Internal UVLO keeps the regulator off until the supply voltage exceeds 7V where internal digital soft starts get initiated to ramp up output. The n NX2142/2142A employs fixed current limiting and FB n UVLO followed by hiccup feature. Other features in- n cludes: 5V gate drive capability , Converter Shutdown by pulling COMP pin to Gnd, Adaptive dead band con- n trol.
Vin +8 to 20V
47uF MMBT3904 1uF
7 6 5 1
DESCRIPTION
FEATURES
Bus voltage operation from 7V to 24V 5V bias regulator available Excellent dynamic response with input voltage feed-forward and voltage mode control Fixed 600kHz, 1MHz switching frequency Internal Digital Soft Start Function Fixed internal hiccup current limit FB UVLO followed by hiccup feature Shutdown by pulling COMP pin low Pb-free and RoHS compliant
APPLICATIONS
Graphic Card on board converters Vddq Supply in mother board applications On board DC to DC such as 12V to 3.3V, 2.5V or 1.8V Set Top Box and LCD Display
TYPICAL APPLICATION
1uF 25TQC33M
BAT54A
VCC REGOUT VIN
BST Hdrv
2
0.1uF AO4800(half)
0.1uF
NX2142
DO3316P-682
9
COMP
SW
10
Vout +3.3V /3A
1000uF,30mohm
20k 27pF 5.2nF
8
Ldrv FB Gnd
3
4
AO4800(half) 1k
324
Figure1 - Typical application of NX2142
ORDERING INFORMATION
Device NX2142CUTR NX2142ACUTR
Rev. 1.1 10/28/07
Temperature 0 to 70o C 0 to 70o C
Package MSOP-10L MSOP-10L
Frequency 600kHz 1MHz
Pb-Free Yes Yes 1
NX2142/2142A
ABSOLUTE MAXIMUM RATINGS
VCC to GND & BST to SW voltage ...................... -0.3V to 6.5V VIN to GND ........................................................ -0.3V to 30V BST to GND Voltage .......................................... -0.3V to 35V SW to GND ....................................................... -2V to 35V REGOUT to GND ................................................ 0.2 to 16V All other pins ..................................................... -0.3V to 6.5V Storage Temperature Range ................................ -65oC to 150oC Operating Junction Temperature Range ................ -40oC to 125oC ESD Susceptibility ............................................ 2kV CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
10-LEAD PLASTIC MSOP
JA 200o C/W
BST 1 HDrv 2 GND 3 LDrv 4 VIN 5 10 SW 9 COMP 8 FB 7 VCC 6 REGOUT
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc =5V, VIN=15V and TA = 0 to 70oC. Typical values refer to TA = 25oC.
PARAMETER Reference Voltage Ref Voltage Ref Voltage line regulation Supply Voltage(Vcc) VCC Voltage Range Operating quiescent current Vcc UVLO VCC-Threshold VCC-Hysteresis Supply Voltage(Vin) Vin Voltage Range Input Voltage Current Vin UVLO Vin-Threshold
Rev. 1.1 10/28/07
SYM VREF
Test Condition
Min
TYP 0.8 0.2 5 3 4.4 0.2
MAX
Units V % V mA V V
VCC IQ
EN=HIGH
VCC_UVLO VCC Rising VCC_Hyst VCC Falling Vin Vin=24V Vin_UVLO Vin Rising 7
25 9 6
V mA V
2
NX2142/2142A
PARAMETER Vin-Hysteresis Oscillator (Rt) Frequency Frequency Over Vin Ramp Peak to Peak Voltage Ramp Valley Voltage Ramp Peak to Peak/Vin Gain Max Duty Cycle Min Duty Cycle Min Controllable on time Error Amplifiers Transconductance Input Bias Current Comp SD threshold Soft Start Soft Start time High Side Driver (CL=3300pF) Output Impedance , Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time Low Side Driver (CL=3300pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current Rise Time Fall Time Deadband Time Fixed OCP OCP voltage threshold FBUVLO Feedback UVLO threshold Over temperature Threshold Hysteresis
Rev. 1.1 10/28/07
N
SYM Vin_Hyst FS
Test Condition Vin Falling NX2142 NX2142A Vin=20V
Min
TYP 0.5 600 1000 1 2 0.8 0.1 77 0
MAX
Units V KHz KHz % V V V/V % % nS umho nA V mS mS
VRAMP
FS=600kHz
150 2500 Ib 0.3 Tss NX2142 NX2142A 3.4 2 100
Rsource(Hdrv) Rsink(Hdrv)
I=200mA I=200mA
1 0.8 50 50 30
ohm ohm ns ns ns
THdrv(Rise) 10% to 90% THdrv(Fall) 90% to 10% Tdead(L to Ldrv going Low to Hdrv going High, 10% to 10% H)
Rsource(Ldrv) Rsink(Ldrv)
I=200mA I=200mA
1 0.5 50 50 30
ohm ohm ns ns ns
TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10%
320 percent of nominal 70 150 20
mV % C C
3
NX2142/2142A
PIN DESCRIPTIONS
PIN SYMBOL VCC PIN DESCRIPTION This pin supplies the internal 5V bias circuit. A 1uF high frequency ceramic X5R capacitor must be placed as close as possible to this pin and ground pin to provide high frequency bypass and to make the 5V regulator stable. This pin supplies voltage to high side FET driver. A minimum 0.1uF ceramic high frequency capacitor is placed as close as possible to and connected to this pin and SW pin. Power ground. This pin is the error amplifiers inverting input. It is connected via resistor divider to the output of the switching regulator to set the output DC voltage. This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop. You can shutdown the switching regulator by pulling this pin below 0.3V. This pin is connected to source of high side FETs and provides return path for the high side driver. This pin also provides input for the OCP comparator by sensing the RDSON of the lower MOSFET. When this pin is below ground by 320mV, both drivers are shutdown and enter hiccup mode. High side gate driver output. Low side gate driver output. The output of the 5V regulator controller that drives a low current low cost external bipolar transistor or an external MOSFET to regulate the voltage at Vcc pin derived from bus voltage. This eliminates an otherwise external regulator needed in applications where 5V is not available. This regulator request a 1uF ceramic X5R type output capacitor in order to be stable. This pin provides the input voltage to the 5V regulator controller as well as the oscillator for the PWM feed forward to work. When VIN exceeds 6V, the converter starts to operate.
BST
GND
FB
COMP
SW
HDRV LDRV
REGOUT
VIN
Rev. 1.1 10/28/07
4
NX2142/2142A
BLOCK DIAGRAM
VIN Ref Regout
4.4/4.2V VCC Bias Generator 1.25V 0.8V UVLO POR START 6V/ 5.5V COMP 0.3V VIN START 0.8V OSC Digital start Up ramp S R FB 0.6V CLAMP START POR 1.3V CLAMP Hiccup Logic OCP comparator SS_half_done 70%*Vp GND FB 320mV Q OC LDRV PWM OC Control Logic VCC SW BST
HDRV
COMP
Figure 2 - Simplified block diagram of the NX2142
Rev. 1.1 10/28/07
5
NX2142/2142A
TYPICAL APPLICATION CIRCUIT
BUS BUS(8-20V)
C10 47u GNDBUS
U _VIN
VDD 7 8 HDRV 2 1
C6 0.1u
U _VCC
C2 1u
D1 BAT54A
Ci1
Q1 2N3904 5 U1 VIN VCC 7
25TQC33M C14 BST 1 BST 1u
C1 0.1u EN_REGOUT 6 2 U_HDRV
M5A STM6912
EN/REG_OUT
HDRV
SW
10
U_SW
SW
Lo 1 2 DO3316P-682
VOUT OUT(5V)
Co1
NX2142CUTR
1000uF, 6.3v,30mohm M6B STM6912 R15 10 5 6
GNDOUT
LDRV
4
U_LDRV
LDRV 4 C9 470p
FB
8
FB
C5 25n R7 10k C4 52p C3 3.3n R10 953 R9
3 R8 1.2k 4.99k COMP 9 COMP
Figure 3- Demo board schematic(VIN=8-20V,VOUT=5V,IOUT=3A)
3
GND
Rev. 1.1 10/28/07
6
NX2142/2142A
Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Quantity 1 1 2 3 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 Reference Ci1 Co1 C1,C6 C2,C14 C3 C4 C5 C9 C10 D1 Lo M5,M6 Q1 R7 R8 R9 R10 R15 U1 Value 25TQC33M 6MV1000W G 0.1u 1u 3.3n 52p 25n 470p 47u BAT54A DO3316P-682 AO4800 MMBT3904 10k 1.2k 4.99k 1% 953 1% 10 NX2142CUTR Manufacture SANYO SANYO
Fairchild Coilcraft AOS Fairchild
NEXSEM INC.
Rev. 1.1 10/28/07
7
NX2142/2142A
Demoboard waveforms
Figure 4 - Output ripple (VIN=12V)
Figure 5 - Output voltage transient response (VIN=12V, IOUT=3A)
Figure 6 - Over current protection
Figure 7 - Startup
100.00% 95.00% 90.00% 85.00% 80.00% Eff(%) 75.00% 70.00% 65.00% 60.00% 55.00% 50.00% 0 500 1000 1500 2000 2500 3000 3500 Iout(mA)
Figure 8 - Output Efficiency(VIN=12V, VOUT=5V)
Rev. 1.1 10/28/07
8
NX2142/2142A
Current Ripple is calculated as
APPLICATION INFORMATION
IRIPPLE =
Symbol Used In Application Information:
VIN VOUT IOUT FS DIRIPPLE - Input voltage - Output voltage - Output current - Switching frequency - Inductor current ripple
VIN -VOUT VOUT 1 x x LOUT VIN FS
=
...(2) 20V-5V 5V 1 x x = 0.919A 6.8uH 20V 600kHz
DVRIPPLE - Output voltage ripple
Output Capacitor Selection
Output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load condition is determined by equation(3).
Design Example
Power stage design requirements: VINMIN=8V VINMAX=20V VOUT=5V IOUT =3A DVRIPPLE <=50mV DVTRAN<=150mV @ 1.5A step FS=600kHz
VRIPPLE = ESR x IRIPPLE +
IRIPPLE 8 x FS x COUT
...(3)
Where ESR is the output capacitors' equivalent series resistance,COUT is the value of output capacitors. Typically when large value capacitors are selected such as Aluminum Electrolytic,POSCAP and OSCON types are used, the amount of the output voltage ripple is dominated by the first term in equation(3) and the second term can be neglected. For this example, Aluminum Electrolytic is chosen as output capacitor, the ESR and inductor current typically determines the output voltage ripple.
Output Inductor Selection
The selection of inductor value is based on inductor ripple current, power rating, working frequency and efficiency. Larger inductor value normally means smaller ripple current. However if the inductance is chosen too large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:
ESRdesire =
VRIPPLE 50mV = = 54m IRIPPLE 0.919A
...(4)
If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 50mV output ripple, Electrolytic
V -V V 1 LOUT = INMAX OUT x OUT x IRIPPLE VINMAX FS IRIPPLE =k xIOUTPUT
where k is between 0.2 to 0.4. Select k=0.3, then
...(1)
6ME1000WG with 30m are chosen.
N=
E S R E x IR I P P L E VR IPPLE
...(5)
Number of Capacitor is calculated as
20V-5V 5V 1 LOUT = x x 0.3 x 3A 20V 600kHz LOUT =6.9uH
Choose LOUT=6.8uH, then coilcraft inductor DO3316P-682HC is a good choice.
Rev. 1.1 10/28/07
N=
30mx 0.919A 50mV
N =0.55 The number of capacitor has to be round up to a integer. Choose N =1. 9
NX2142/2142A
If ceramic capacitors are chosen as output capacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors. For example, one 100uF, X5R ceramic capacitor with 2m ESR is used. The amount of output ripple is tance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected output inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the ESR of output capacitor. For low frequency capacitor such as electrolytic capacitor, the product of ESR and capacitance is high and L L crit is true. In that case, the transient spec is mostly like to dependent on the ESR of capacitor. Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following
N= ESR E x Istep Vtran + VOUT x 2 2 x L x C E x Vtran
VRIPPLE
0.919A = 2mx 0.919A + 8 x 600kHz x100uF = 1.838mV + 1.9mV = 3.738mV
One ceramic capacitors are needed. Although this can meet DC ripple spec, however it needs to be studied for transient requirement. Based On Transient Requirement Typically, the output voltage droop during transient is specified as V droop < V tran @step load DISTEP During the transient, the voltage droop during the transient is composed of two sections. One section is dependent on the ESR of capacitor, the other section is a function of the inductor, output capacitance as well as input, output voltage. For example, for the overshoot when load from high load to light load with a DISTEP transient load, if assuming the bandwidth of system is high enough, the overshoot can be estimated as the following equation.
...(9)
where
0 if L L crit = L x Istep - ESR E x CE V OUT
if
L L crit
...(10)
For example, assume voltage droop during transient is 150mV for 1.5A load step. If the Electrolytic 6ME1000WG(1000uF, 30mohm ESR) is used, the crticial inductance is given as
L crit =
ESR E x C E x VOUT = Istep
30m x 1000F x 5V = 100H 1.5A
The selected inductor is 6.8uH which is much smaller than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance. number of capacitor is
Vovershoot
where
VOUT = ESR x Istep + x 2 2 x L x COUT
...(6)
is the a function of capacitor,etc.
L L crit
...(7)
0 if L L crit = L x Istep - ESR x COUT V OUT
where
L crit =
if
N= =
ESR E x Istep Vtran
ESR x COUT x VOUT ESR E x C E x VOUT = ...(8) Istep Istep
30m x1.5A 200mV = 0.225
The number of capacitors has to satisfy both ripple and transient requirement. Overall, we choose N=1.
where ESRE and CE represents ESR and capaci-
Rev. 1.1 10/28/07
10
NX2142/2142A
It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters. following figures and equations show how to realize the type III compensator by transconductance amplifier.
FZ1 = FZ2 = FP1 = FP2 =
1 2 x x R 4 x C2 1 2 x x (R 2 + R3 ) x C3 1 2 x x R3 x C3 1 2 x x R4 x C1 x C2 C1 + C2
...(11) ...(12) ...(13) ...(14)
Compensator Design
Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, the Bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crossing 0dB with -20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should be chosen. Voltage feedforward compensation is used in NX2142 to compensate the output voltage variation caused by input voltage changing. The feedforward funtion is realized by using VIN pin voltage to program the oscillator ramp voltage VOSC at about 1/10 of VIN voltage, which provides nearly constant power stage gain under wide voltage input range.
where FZ1,FZ2,FP1 and FP2 are poles and zeros in the compensator. The transfer function of type III compensator for transconductance amplifier is given by:
Ve 1 - gm x Z f = VOUT 1 + gm x Zin + Z in / R1
For the voltage amplifier, the transfer function of compensator is
Ve -Z f = VOUT Zin
To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R4>>2/gm. And it would be desirable if R1||R2||R3>>1/gm can be met at the same time,
Zin R3
Vout
Zf C1 C2 Fb gm Ve R4
R2 C3 R1
A. Type III compensator design
For low ESR output capacitors, typically such as Sanyo oscap and poscap, the frequency of ESR zero caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The
Rev. 1.1 10/28/07
Vref
Figure 9 - Type III compensator using transconductance amplifier 11
NX2142/2142A
Case 1: FLCGain(db)
power stage
C2 =
FLC
40dB/decade
=
1 2 x x FZ1 x R 4
1 2 x x 0.5 x 9.2kHz x 10k = 3.5nF
loop gain
Choose C2=3.9nF. 4. Calculate C1 by equation (14) with pole Fp2 at
FESR
20dB/decade compensator
half the switching frequency.
C1 = =
1 2 x x R 4 x FP2
1 2 x x 10k x 300kHz = 53pF
Choose C1=52pF. 5. Calculate C3 with the crossover frequency at
FZ1 FZ2
FO FP1
FP2
1/10~ 1/5 of the switching frequency. Set FO=60kHz.
C3 =
Figure 10 - Bode plot of Type III compensator (FLCVOSC 2 x x FO x L x x C out Vin R4
1 2 x x 60kHz x 6.8uH x x 44uF 10 10k =1.1nF =
Choose C3=1.2nF. 6. Set zero FZ2 = 0.75FLC and Fp1 =0.5Fs, calculate R2.
wih3m is chosen as output capacitor, output inductor t
is 6.8uH. 1. Calculate the location of LC double pole FLC and ESR zero FESR.
R2 = =
1 11 x( - ) 2 xx C3 Fz2 Fp1
FLC = =
1 2 x x L OUT x C OUT 1
1 1 1 x( ) 2 xx 1.2nF 0.75*9.2kHz 300kHz =18k
Choose R2=20k. 7. Calculate R3 by equation (13) with Fp1 =Fs.
2 x x 6.8uH x 44uF = 9.2kHz
R3 = =
FESR = =
1 2 x x ESR x C OUT
1 2 x x FP1 x C3
1 2 x x 1.5m x 44uF = 241kHz
Rev. 1.1 10/28/07
1 2 x x 600kHz x 1.2nF = 221
Choose R3 =300. 12
NX2142/2142A
8. Calculate R1.
R x VREF 20k x 0.8V R1 = 2 = = 5.7k VOUT -VREF 5V-0.8V
Choose R1=5.7k.
FESR = =
1 2 x x ESR x COUT
1 2 x x 30m x 1000uF = 5.3kHz
2. Set R4 equal to 10k.
Case 2:
FLC3. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11).
Gain(db)
power stage
FLC
40dB/decade
C2 = =
1 2 x x FZ1 x R 4
FESR
loop gain
1 2 x x 0.75 x 1.93kHz x 10k = 10nF
Choose C2=10nF. 4. Calculate C1 by equation (14) with pole Fp2 at
20dB/decade compensator
half the switching frequency.
C1 = =
1 2 x x R 4 x FP2
1 2 x x 10k x 300kHz = 53pF
FZ1 FZ2 FP1 FO
(FLCFP2
Choose C1=52pF. 5. Calculate C3 with the crossover frequency at 1/10~ 1/5 of the switching frequency. Set FO=60kHz. C3 = VOSC FO x L x V in E S R x R 4 x FP 1
Figure 11 - Bode plot of Type III compensator
If electrolytic capacitors are used as output capacitors, typical design example of type III compensator in which the crossover frequency is selected as FLC1 60kHz x 6.8uH x 10 30m x 10k x 5.3kHz =25nF = Choose C3=25nF. 6. Set zero FZ2 = FLC and Fp1 =FESR, calculate R2.
R2 = =
1 11 x( ) 2 x x C3 Fz2 Fp1
FLC = =
1 2 x x LOUT x COUT 1
1 1 1 x( ) 2 x x 25nF 1.93kHz 5.3kHz =2k
Choose R2=20k. 7. Calculate R3 by equation (13) with Fp1 =FESR.
2 x x 6.8uH x 1000uF = 1.93kHz
Rev. 1.1 10/28/07
13
NX2142/2142A
R3 = = 1 2 x x FP1 x C3
Gain(db)
1 2 x x 5.3kHz x 25nF = 1.2k
Choose R3 =1.2k. 8. Calculate R1.
power stage 40dB/decade loop gain 20dB/decade
R1 =
R 2 x VREF 1.2k x 0.8V = = 381 VOUT -VREF 5V-0.8V
Choose R1=381.
B. Type II compensator design
If the electrolytic capacitors are chosen as power stage output capacitors, usually the Type II compensator can be used to compensate the system. For this type of compensator, FO has to satisfy FLCcompensator Gain
FZ FLC FESR
FO FP
Figure 12 - Bode plot of Type II compensator Case 1: Type II compensator can be realized by simple RC circuit as shown in figure 13. R3 and C1 introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise. To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R3>>1/gm and R1||R2>>1/gm. The following equations show the compensator pole zero location and constant gain.
Vout R2 Fb R1 Vref R3 C2 C1
gm
Ve
R Gain= 3 R2 Fz = 1 2 x x R3 x C1
... (15) ... (16) ... (17)
Figure 13 - Type II compensator with transconductance amplifier(case 1) The following parameters are used as an example for type II compensator design, three 1500uF with 19mohm Sanyo electrolytic CAP 6MV1500WGL are used as output capacitors. Coilcraft DO5010P-152HC 1.5uH is used as output inductor. The power stage information is that: VIN=12V, VOUT=1.2V, IOUT =12A, FS=600kHz. 1.Calculate the location of LC double pole FLC and ESR zero FESR.
1 Fp 2 x x R 3 x C2
Rev. 1.1 10/28/07
14
NX2142/2142A
FLC = = 1 2 x x L OUT x COUT 1
Case 2: Type II compensator can also be realized by simple RC circuit without feedback as shown in figure 15. R3 and C1 introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise. The following equations show the compensator pole zero location and constant gain.
2 x x 1.5uH x 4500uF = 1.94kHz
FESR =
1 2 x x ESR x COUT
1 = 2 x x 6.33m x 4500uF = 5.6kHz
2.Set crossover frequency FO=60kHz>>FESR. 3. Set R2 equal to 4k. Based on output voltage, using equation 21, the final selection of R1 is 8k. 4.Calculate R3 value by the following equation.
Gain=gm x Fz =
R1 x R3 R1 +R 2
... (18) ... (19) ... (20)
1 2 x x R3 x C1 1 2 x x R 3 x C2
Fp
Vout R2 Fb gm R1 Vref Ve R3 C2 C1
R3= =
VOSC 2 x x FO x L x xR2 V in ESR
1 2 x x 60kHz x 1.5uH x x 4k 10 6.33m =36k
Choose R3 =37.4k. 5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole.
C1= = 1 2 x x R3 x Fz
Figure 14 - Type II compensator with transconductance amplifier(case 2) The following is parameters for type II compensator design. Input voltage is 12V, output voltage is 2.5V, output inductor is 2.2uH, output capacitors are two 680uF with 41m electrolytic capacitors. 1.Calculate the location of LC double pole FLC and ESR zero FESR.
1 2 x x 37.4k x 0.75 x 1.94kHz =2.7nF
Choose C1=2.7nF. 6. Calculate C2 by setting compensator pole Fp at half the swithing frequency.
1 C2= x R 3 x Fs = 1 x 3 7 .4k x 6 0 0 k H z =14pF
FLC = =
1 2 x x L OUT x COUT 1
Choose C2=15pF.
2 x x 2.2uH x 1360uF = 2.9kHz
Rev. 1.1 10/28/07
15
NX2142/2142A
FESR = = 1 2 x x ESR x COUT
Output Voltage Calculation
Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at 0.8V. The divider consists of two ratioed resistors so that the output voltage applied at the Fb pin is 0.8V when the output voltage is at the desired value. The following equation applies to figure 15, which shows the relationship between vider.
1 2 x x 20.5m x 1360uF = 5.7kHz
2.Set R2 equal to10k. Using equation 18, the final selection of R1 is 4.7k. 3. Set crossover frequency at 1/10~ 1/5 of the swithing frequency, here FO=60kHz. 4.Calculate R3 value by the following equation.
VOUT , VREF and voltage di-
Vout R2 Fb R1 Vref Figure 15 - Voltage divider
R 2 x VR E F V O U T -V R E F
R3 = =
VOSC 2 x x FO x L 1 VOUT x x x Vin RESR gm VREF
1 2 x x 60kHz x 2.2uH 1 x x 10 20.5m 2.5mA/V 2.5V x 0.8V =5k
Choose R3 =5k. 5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole.
R 1=
...(21)
C1 = =
1 2 x x R 3 x Fz
where R2 is part of the compensator, and the value of R1 value can be set by voltage divider.
1 2 x x 5k x 0.75 x 2.9kHz =14nF
Choose C1=15nF. 6. Calculate C2 by setting compensator pole Fp at half the swithing frequency.
C = = 1 xR
3
Input Capacitor Selection
Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high frequency noise.The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors can be calculated as:
2
x Fs
1 x 5k x 600kH z =54pF
Choose C2=52pF.
IRMS = IOUT x D x 1- D D= VOUT VINMIN
...(22)
VINMIN = 8V, VOUT=1.05V, IOUT=10A, the result of input RMS current is 3.4A. For higher efficiency, low ESR capacitors are recommended. One Sanyo OSCON CAP 25SVP56M
Rev. 1.1 10/28/07
16
NX2142/2142A
25V 56uF 28m with 3.8A RMS rating are chosen as input bulk capacitors. where QHGATE is the high side MOSFETs gate charge,QLGATE is the low side MOSFETs gate charge,VHGS is the high side gate source voltage, and VLGS is the low side gate source voltage. This power dissipation should not exceed maximum power dissipation of the driver device.
Power MOSFETs Selection
The NX2142 requires two N-Channel power MOSFETs. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, maximum current rating, MOSFET on resistance and power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall converter efficiency. In this design example, two STM6912 are used. They have the following parameters: VDS=30V, ID =6A,RDSON =57m,QGATE =6.3nC. There are two factors causing the MOSFET power loss:conduction loss, switching loss. Conduction loss is simply defined as:
Over Current Limit Protection
Over current Limit for step down converter is achieved by sensing current through the low side MOSFET. For NX2142, the current limit is decided by the RDSON of the low side mosfet. When synchronous FET is on, and the voltage on SW pin is below 320mV, the over current occurs. The over current limit can be calculated by the following equation.
PHCON =IOUT 2 x D x RDS(ON) x K PLCON =IOUT 2 x (1 - D) x RDS(ON) x K PTOTAL =PHCON + PLCON
...(23)
ISET = 320mV/R DSON
The MOSFET RDSON is calculated in the worst case situation, then the current limit for MOSFET STM6912 is
ISET = 320mV 320mV = = 4.6A RDSON 1.2 x 57m
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature dependency. As a result, RDS(ON) should be selected for the worst case, in which K approximately equals to 1.4 at 125oC according to datasheet. Conduction loss should not exceed package rating or overall system thermal budget. Switching loss is mainly caused by crossover conduction at the switching transition. The total switching loss can be approximated.
Layout Considerations
The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. There are two sets of components considered in the layout which are power components and small signal components. Power components usually consist of input capacitors, high-side MOSFET, low-side MOSFET, inductor and output capacitors. A noisy environment is generated by the power components due to the switching power. Small signal components are connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended . Layout guidelines: 1. First put all the power components in the top layer connected by wide, copper filled areas. The input capacitor, inductor, output capacitor and the MOSFETs should be close to each other as possible. This helps 17
1 x VIN x IOUT x TSW x FS ...(24) 2 where IOUT is output current, TSW is the sum of TR and TF which can be found in mosfet datasheet, and FS is switching frequency. Swithing loss PSW is frequency dependent. Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET. MOSFET gate driver loss is the loss generated by dischar ging the gate capacitor and is dissipated in driver circuits.It is proportional to frequency and is defined as: PSW =
Pgate = (QHGATE x VHGS + QLGATE x VLGS ) x FS
Rev. 1.1 10/28/07
...(25)
NX2142/2142A
to reduce the EMI radiated by the power loop due to the high switching currents through them. 2. Low ESR capacitor which can handle input RMS ripple current and a high frequency decoupling ceramic cap which usually is 1uF plane connection is a must. 3. The output capacitors should be placed as close as to the load as possible and plane connection is required. 4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a plane ans as close as possible. A snubber nedds to be placed as close to this junction as possible. 5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not enough. This is very important. The same applies to the output capacitors and input capacitors. 6. Hdrv and Ldrv pins should be as close to MOSFET gate as possible. The gate traces should be wide and short. A place for gate drv resistors is needed to fine tune noise if needed. 7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divider. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. All GNDs need to go directly thru via to GND plane. 10. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. 11. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function.
need to be practi-
cally touching the drain pin of the upper MOSFET, a
Rev. 1.1 10/28/07
18

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